Implement the following two functions jointly into a Programmable Logic Array (PLA) using gate-level diagram similar to the one in Figure B.27. X = A.B’.D + A’.C’ + C’.D’ Y = A’.C’.D’ + C’.D’ + B.C + A’.C’.D Note that the PLA has only 4 AND gates. So it can only generate 4 different product terms. You may need to simplify the functions in order to incorporate all the product terms into the PLA. To simplify your figure, you may draw the PLA in customary schematic as shown in Figure B.27 in textbook.
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